With the development of IC chip technology, chip packaging technology has also reached a new level, and system integration can be realized on a single chip.  

 

Among the many new packaging technologies, wafer-level packaging technology is the most innovative and most eye-catching, and is a symbol of revolutionary breakthroughs in packaging technology. The concept of wafer-level packaging technology is to fabricate CSP packaging technology on the entire wafer, which is to complete most of the packaging work at the wafer level. Therefore, the wafer-level package structure can omit the step of flip chip technology dispensing. At present, an elastomer or an elastomer-like body can be used to offset the stress, and the process of these elastomers can be completed on the entire wafer. Eliminates the complicated process of dispensing separate components. The design concept of square wafer packaging technology is to increase the distance between components and substrates, that is, to select a larger tin-lead solder ball to achieve conductivity. The existing wafer-level packaging technology uses re-layout technology to add The spacing of the large tin-lead solder balls is such as to increase the volume of the tin-lead solder balls, thereby reducing and withstanding the stress caused by the difference in thermal expansion between the substrate and the components, thereby improving the reliability of the components.

Wafer-level packaging and wafer-level chip-scale packaging (WLCSP) are the same concept. It is a breakthrough in chip-scale packaging. It represents a type of package that still exists as a wafer after the completion of a circuit package. The main reason is that it can reduce the package size to the same size as IC chips and the cost of processing. Wafer-level packaging is currently growing at an alarming rate, with an average annual growth rate (CAGR) of 210%. The growing devices are primarily integrated circuits, passive components, high-performance memories, and devices with fewer pin counts.

There are currently five proven process technologies available for wafer bumps, each with its own advantages and disadvantages. Among them, gold wire post bumps and electrolytic or electroless gold plating bumps are mainly used for packages with a small number of pins (generally less than 40). Applications include glass flip chip (COG) and soft film flip chip (COF). ) and RF modules. Due to the high cost and long process time of such technical materials, it is not suitable for packages with many I/O pins. Another technique is to place the solder balls first and then reflow the pre-formed solder balls. This technique is suitable for packages with up to 300 pins. The two most commonly used wafer bump processes are electrolytic or chemically plated solders, as well as solder paste printing using high precision imprinting platforms.